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CY62147EV30 MoBL(R)
4-Mbit (256K x 16) Static RAM
Features
Very high speed: 45 ns Temperature ranges Industrial: -40 C to +85 C Wide voltage range: 2.20 V to 3.60 V Pin compatible with CY62147DV30 Ultra low standby power Typical standby current: 1 A Maximum standby current: 7 A (Industrial) Ultra low active power Typical active current: 2 mA at f = 1 MHz [1] and OE features Easy memory expansion with CE

also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when:

Deselected (CE HIGH) Outputs are disabled (OE HIGH) Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) Write operation is active (CE LOW and WE LOW)
Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed and power Available in Pb-free 48-ball very fine ball grid array (VFBGA) (single/dual CE option) and 44-pin thin small outline package (TSOP) II packages Byte power-down feature
Functional Description
The CY62147EV30 is a high performance CMOS static RAM (SRAM) organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery LifeTM (MoBL) in portable applications such as cellular telephones. The device
To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Logic Block Diagram
DATA IN DRIVERS
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
256K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER BHE WE [1] CE OE BLE
POWER DOWN CIRCUIT
CE
A12
A13
A15
Note 1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
Cypress Semiconductor Corporation Document Number: 38-05440 Rev. *J
*
198 Champion Court
A11
A17
A14
A16
BHE BLE
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 31, 2011
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Contents
Product Portfolio .............................................................. 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance........................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16
Document Number: 38-05440 Rev. *J
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Product Portfolio
Product Range Min 2.2 VCC Range (V) Typ[2] 3.0 Max 3.6 Speed (ns) Power Dissipation Operating ICC (mA) Standby ISB2 (A) f = 1 MHz f = fmax Typ[2] Max Typ[2] Max Typ[2] Max 2 2.5 15 20 1 7
CY62147EV30LL
Industrial
45 ns
Pin Configuration
Figure 1. 48-Ball VFBGA (Single Chip Enable) [3, 4]
1 BLE I/O8 I/O9 2 OE BHE I/O10 3 A0 A3 A5 A17 NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
Figure 2. 48-Ball VFBGA (Dual Chip Enable)[3, 4]
1 BLE I/O8 I/O9 2 OE BHE I/O10 3 A0 A3 A5 A17 NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
VSS I/O11 VCC I/O12
VSS I/O11 VCC I/O12
I/O14 I/O13 A14 I/O15 NC NC A8 A12 A9
I/O14 I/O13 A14 I/O15 NC NC A8 A12 A9
Figure 3. 44-Pin TSOP II [3]
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12
Notes 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 3. NC pins are not connected on the die. 4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
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Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature ............................... -65 C to + 150 C Ambient temperature with power applied ......................................... -55 C to + 125 C Supply voltage to ground potential .......................... -0.3 V to + 3.9 V (VCCmax + 0.3 V) DC voltage applied to outputs in High Z state [5, 6] .............. -0.3 V to 3.9 V (VCCmax + 0.3 V) DC input voltage [5, 6] ........... -0.3 V to 3.9 V (VCCmax + 0.3 V) Output current into outputs (LOW) ............................. 20 mA Static discharge voltage .......................................... >2001 V (MIL-STD-883, method 3015) Latch-up current ...................................................... >200 mA
Operating Range
Device CY62147EV30LL Range Ambient Temperature VCC [7] Industrial -40 C to +85 C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current Automatic CE power-down current -- CMOS inputs Test Conditions IOH = -0.1 mA IOH = -1.0 mA, VCC > 2.70 V IOL = 0.1 mA IOL = 2.1 mA, VCC = 2.70 V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V GND < VI < VCC GND < VO < VCC, output disabled f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA f = 1 MHz CMOS levels CE > VCC - 0.2 V VIN > VCC - 0.2 V, VIN < 0.2 V f = fmax (address and data only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60 V 45 ns (Industrial) Min 2.0 2.4 - - 1.8 2.2 -0.3 -0.3 -1 -1 - - - Typ [8] - - - - - - - - - - 15 2 1 Max - - 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 20 2.5 7 A Unit V V V V V V V V A A mA
ISB1
ISB2 [9]
Automatic CE CE > VCC - 0.2 V power-down VIN > VCC - 0.2 V or VIN < 0.2 V, current -- CMOS f = 0, VCC = 3.60 V inputs
-
1
7
A
Capacitance
For all packages.[10] Parameter CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 5. VIL(min) = -2.0 V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 9. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 10. Tested initially and after any design or process changes that may affect these parameters.
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Thermal Resistance[11]
Parameter JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Figure 4. AC Test Load and Waveforms VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board VFBGA Package 75 10 TSOP II Package 77 13 Unit C / W C / W
Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH V 3.0 V 1103 1554 645 1.75 Unit V
Parameters R1 R2 RTH VTH
2.50 V 16667 15385 8000 1.20
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR[13] tCDR [11] tR [14] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time VCC= 1.5 V, CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V Conditions Min 1.5 - 0 45 Typ [12] Max Unit - 0.8 - - - 7 - - V A ns ns
Figure 5. Data Retention Waveform[15, 16]
DATA RETENTION MODE VCC CE or BHE.BLE
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
Notes 11. Tested initially and after any design or process changes that may affect these parameters 12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 13. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.. 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 15. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 16. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
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Switching Characteristics
Over the Operating Range [17, 18] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[21]
Description
45 ns (Industrial) Min Max
Unit
Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to LOW Z[19] OE HIGH to High Z CE LOW to Low Z
[19, 20]
45 - 10 - - 5 - 10 - 0 - - 10 -
- 45 - 45 22 - 18 - 18 - 45 45 - 18
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
[19]
CE HIGH to High Z[19, 20] CE LOW to power-up CE HIGH to power-down BLE/BHE LOW to data valid BLE/BHE LOW to Low Z[19] BLE/BHE HIGH to HIGH Z[19, 20]
Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width BLE/BHE LOW to write end Data setup to write end Data hold from write end WE LOW to High Z[19, 20] WE HIGH to Low Z[19]
45 35 35 0 0 35 35 25 0 - 10
- - - - - - - - - 18 -
ns ns ns ns ns ns ns ns ns ns ns
Notes 17. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Load and Waveforms on page 5. 18. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 21. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 6. Read Cycle No. 1: Address Transition Controlled[22, 23] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID Figure 7. Read Cycle No. 2: OE Controlled[23, 24, 25] tAA DATA VALID
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes 22. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 23. WE is HIGH for read cycle. 24. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 25. Address valid before or similar to CE and BHE, BLE transition LOW.
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Switching Waveforms (continued)
Figure 8. Write Cycle No. 1: WE Controlled[26, 27, 28, 29]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE DATA I/O
NOTE 30
tSD DATAIN tHZOE
tHD
Figure 9. Write Cycle No. 2: CE Controlled[26, 27, 28, 29]
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA I/O
NOTE 30
tHD
DATAIN tHZOE
Notes 26. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 27. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 28. Data I/O is high impedance if OE = VIH. 29. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 30. During this period, the I/Os are in output state. Do not apply input signals.
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Switching Waveforms (continued)
Figure 10. Write Cycle No. 3: WE Controlled, OE LOW[31, 32]
tWC ADDRESS tSCE CE
BHE/BLE tAW WE tSA
tBW tHA tPWE
tSD DATA I/O
NOTE 33
tHD
DATAIN tHZWE tLZWE
Figure 11. Write Cycle No. 4: BHE/BLE Controlled, OE LOW[31, 32]
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE
tHZWE
tHA tBW
tPWE tSD DATAIN
tLZWE
tHD
DATA I/O
NOTE 33
Notes 31. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 32. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 33. During this period, the I/Os are in output state. Do not apply input signals.
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Truth Table
CE[34, 35] H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H High Z High Z Data out (I/O0-I/O15) Data out (I/O0-I/O7); I/O8-I/O15 in High Z Data out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data in (I/O0-I/O15) Data in (I/O0-I/O7); I/O8-I/O15 in High Z Data in (I/O8-I/O15); I/O0-I/O7 in High Z I/Os Mode Deselect/Power-down Deselect/Power -down Read Read Read Output disabled Output disabled Output disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Notes 34. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 35. For the Dual Chip Enable device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels is not permitted on any of the Chip Enable pins (CE for the Single Chip Enable device; CE1 and CE2 for the Dual Chip Enable device).
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CY62147EV30 MoBL(R)
Ordering Information
Speed (ns) 45 Ordering Code CY62147EV30LL-45BVI CY62147EV30LL-45BVXI CY62147EV30LL-45B2XI CY62147EV30LL-45ZSXI Package Diagram Package Type Operating Range Industrial 51-85150 48-Ball Very Fine Pitch Ball Grid Array [36] 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) [36] 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) [37] 51-85087 44-Pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 4 7 E V30 LL 45 xxx I Temperature Range: I = Industrial Package Type: ZSX = TSOP II (Pb-free), BVX = VFBGA (Pb-free) etc Speed Grade Low Power Voltage Range (3V Typical) E = Process Technology 90 nm Buswidth = x 16 Density = 4-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress
Notes 36. This BGA package is offered with single chip enable. 37. This BGA package is offered with dual chip enable.
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Package Diagrams
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150 *F
51-85150 *F
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Package Diagrams (continued)
Figure 13. 44-Pin TSOP II, 51-85087
51-85087 *C
Acronyms
Acronym CMOS I/O SRAM VFBGA TSOP input/output static random access memory very fine ball grid array thin small outline package Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol C A mA MHz ns pF V W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts
Document Number: 38-05440 Rev. *J
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Document History Page
Document Title: CY62147EV30 MoBL(R) 4-Mbit (256K x 16) Static RAM Document Number: 38-05440 Rev. ** *A ECN No. 201861 247009 Orig. of Change AJU SYT Submission Date 01/13/04 See ECN New Data Sheet Changed from Advanced Information to Preliminary Moved Product Portfolio to Page 2 Changed Vcc stabilization time in footnote #8 from 100 s to 200 s Removed Footnote #15(tLZBE) from Previous Revision Changed ICCDR from 2.0 A to 2.5 A Changed typo in Data Retention Characteristics(tR) from 100 s to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages Changed from Preliminary information to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Removed 35ns Speed Bin, "L" version of CY62147EV30 Changed ball E3 from DNU to NC. Removed redundant foot note on DNU. Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A. Changed ICCDR from 2.5 A to 7 A. Added ICCDR typical value. Changed AC test load capacitance from 50 pF to 30 pF on Page #4, changed tLZOE from 3 ns to 5 ns, changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns, changed tHZCE from 22 ns to 18 ns, changed tPWE from 30 ns to 35 ns and changed tSD from 22 ns to 25 ns. Updated the package diagram 48-pin VFBGA from *B to *D Updated the ordering information table and replaced the Package Name column with Package Diagram. Included Automotive Range in product offering Updated the Ordering Information Added Preliminary Automotive-A information Added footnote #9 related to ISB2 and ICCDR Added footnote #14 related AC timing parameters Converted Automotive-A and Automotive -E specs from preliminary to final Added -45B2XI part (Dual CE option) Added CY62147EV30LL-45ZSXA in the ordering information table Updated package diagrams. Added Contents. Updated links in Sales, Solutions, and Legal Information. Added Note 23. Changed Table Footnotes to Footnotes. Added Ordering Code Definitions. Description of Change
*B
414807
ZSD
See ECN
*C *D
464503 925501
NXR VKN
See ECN See ECN
*E *F *G *H
1045701 2577505 2681901 2886488
VKN VKN/PYRS VKN/PYRS AJU
See ECN 10/03/08 04/01/09 03/02/2010
*I
3109050
12/13/2010
PRAS
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Document Title: CY62147EV30 MoBL(R) 4-Mbit (256K x 16) Static RAM Document Number: 38-05440 Rev. *J ECN No. 3123973 Orig. of Change RAME Submission Date 01/31/2011 Description of Change Separated Industrial and Auto parts from this datasheet Removed Automotive info Added Acronyms and Units of Measure table
Document Number: 38-05440 Rev. *J
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05440 Rev. *J
Revised January 31, 2011
Page 16 of 16
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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Price & Availability of CY62147EV30LL-45B2XI

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